It is well-known that applying appropriate compressive stress to the channel of a P-type field-effect transistor (PFET) and appropriate tensile stress to the channel of an N-type field-effect transistor (NFET) drastically improves channel performance. This is usually accomplished by disposing a compressive silicon nitride (SiN) layer over a PFET and a tensile SiN layer over an NFET.
For example, referring to FIG. 1, an NFET and a PFET (also referred to herein as NFET A and PFET A) are disposed on a silicon layer 100. The portion of silicon layer 100 shown is divided into a P-well 101 and an N-well 102. In addition, the NFET and PFET are isolated from neighboring components with a shallow-trench isolation layer 106, and are also covered with a dielectric material 103. A tensile SiN layer 104 covers the NFET, and a compressive SiN layer 105 covers the PFET. Tensile and compressive layers 104, 105 contact each other at a tensile-compressive (T-C) boundary. The NFET and PFET share a common polysilicon gate 108, which extends across the T-C boundary, which is electrically connected to a conductive plug 107 that allows electrical connection of common gate 108 to other portions of the circuitry.
As can be seen in FIG. 1, tensile and compressive layers 104, 105 slightly overlap each other at the T-C boundary. This is a result of the manufacturing process typically used to form tensile and compressive layers 104, 105. The overlap is considered desirable as it prevents unintentional etching of structures disposed below layers 104, 105. However, where conductive plug 107 is co-located with the T-C boundary as shown in FIG. 1, the overlap can cause problems. In particular, referring to FIGS. 5 and 6, when forming conductive plug 107 (which may be formed of, for example, tungsten (W)) using traditional manufacturing processes, one or more conductive “subways” 501, 502 may be formed that extend parallel to and on opposing sides of the T-C boundary. These subways 501, 502 are essentially conductive material that leaks through tunnels created between compressive and tensile layers 104, 105.
Techniques for reducing the size of semiconductor devices include placing plug 107 and other similar plugs on the T-C boundary and configuring NFET/PFET pairs to share common gates. However, this can cause problems. For instance, where another plug 601 for another gate 602 common to a second NFET/PFET pair (NFET B and PFET B, the positions of which are roughly indicated with broken circles) is also co-located with the T-C boundary, there is a significant likelihood that subway 501 and/or subway 502 will electrically connect plug 107 with plug 601. This is extremely undesirable as plug 107 and plug 601 should be able to be at different voltages from each other as desired. Thus, subways 501 and/or 502 may act as unintended short-circuits in a significant percentage of manufactures devices having the shown configuration.
One possibility would be to prohibit locating contacts near the T-C boundary. However, this rule would drastically increase chip size. This is not a practical option.